The present invention relates broadly to digital filters and in particular to a combinatorial digital filter apparatus of the second order.
In the present state of art, digital filters have become increasingly attractive as replacements for analog filters due to recent advances in semi-conductor technology. As the speed of machine operations increase, either to permit real time processing of wideband signals or to time-share the arithmetic unit, there is a resultant rapid increase in hardware complexity, as measured by the number of IC's used, and in power consumption. The major factor causing this increase, lies with the wide spread use high speed multipliers to perform the required operations.
Researchers in the field have proposed an approach to the implementation of digital filters that is well suited to LSI construction. These technological advances center about a very efficient serial multiplier that produces a rounded binary number, and lends itself particularly well to multiplexed circuit operation. Using current TTL technology, multipliers of this type can accommodate a bit rate of approximately 25 MHz. The present invention provides a new approach for the hardware implementation of fixed point arithmetic digital filters. The new realization calls for the storing of the finite number of possible outcomes of an intermediate arithmetic operation, and using them to obtain the next output sample through repeated addition and shifting operations, thereby no multiplications are required. In addition, the present approach provides digital filters which operate at speeds that are difficult or impossible to achieve with the existing state of the art.